DocumentCode
1807949
Title
The reduction of sampling noise in switched-capacitor circuits through spatial oversampling
Author
Hong, Merit Y.
Author_Institution
Semicond. Products Sector, Motorola Inc., Tempe, AZ, USA
Volume
4
fYear
2002
fDate
2002
Abstract
A fundamental limit to the switched-capacitor design of A/D converters has been thought to be the sampling or kT/C noise on the input capacitor. Such a limitation imposes a lower bound on capacitor sizes, and hence an upper bound on the maximum possible sampling rate. However, it is shown here that sampling noise need not be a fundamental limit, and that many times the performance of existing A/D converters is possible.
Keywords
analogue-digital conversion; circuit noise; signal sampling; switched capacitor networks; A/D converters; ADC; SC circuit design; capacitor mismatch; design technique; kT/C noise; sampling noise reduction; spatial oversampling; switched-capacitor circuits; Circuit noise; Equations; Noise reduction; Sampling methods; Semiconductor device noise; Signal sampling; Switched capacitor circuits; Switching converters; Upper bound; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010531
Filename
1010531
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