Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects

Author

Eble, John C. ; De, Vivek K. ; Wills, D. Scott ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

56

Lastpage

58

Abstract

Optimal repeater insertion in long interconnects is used to minimize the interconnect response time by mitigating the effects of resistance. The use of this scheme in future high clock frequency designs can lead to an alarming number of required repeaters as predicted by a compact expression for the total number of repeaters. Novel design equations, which significantly decrease the number and power dissipation of these drivers, are derived that minimize the repeater number, size, energy dissipation, or energy-delay product

Keywords

ULSI; circuit optimisation; delays; integrated circuit design; integrated circuit interconnections; minimisation; repeaters; timing; GSI interconnects; clock frequency; design equations; drivers; gigascale integration interconnects; interconnect response time; long interconnects; minimization; optimal repeater insertion; power dissipation; repeater count; repeater energy dissipation; repeater energy-delay product; repeater size; repeaters; resistance effects; Clocks; Contracts; Delay estimation; Energy dissipation; Equations; Frequency; Repeaters; Stochastic processes; Timing; Wire;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704750

Filename

704750