Title :
Two methods to enhance the master thread´s performance in SMT Chip
Author :
Pengyong, Ma ; Shuming, Chen ; Xiao, Hu
Author_Institution :
Nat. Univ. of Defense Technol., Changsha
Abstract :
In SMT processor, every thread´s executing time will be enlarged due to sharing resource by several threads. It will result in task lost in real time system. In this paper, we present two methods to alleviate the cache conflict in multithread chip, one is protecting the last instructions of master thread, and the other is locking loop. Both methods only need several additional registers. Simulations show that not only the performance of master thread is improved by 14%, but also the IPC of all threads is improved about 6%.
Keywords :
microprocessor chips; multi-threading; SMT chip; SMT processor; cache conflict; master thread performance; multithread chip; resource sharing; simultaneous multithreading chips; Computer science; Costs; Hardware; Parallel processing; Protection; Real time systems; Registers; Statistics; Surface-mount technology; Yarn;
Conference_Titel :
Network and Parallel Computing Workshops, 2007. NPC Workshops. IFIP International Conference on
Conference_Location :
Liaoning
Print_ISBN :
978-0-7695-2943-1
DOI :
10.1109/NPC.2007.45
