A novel semiconductor test equipment concept: automatic test equipment with computational intelligence technique (ATE-CIT)

Semiconductor automatic test equipment (ATE) analyses the responses from the semiconductor chip based on a set of pre-defined lest patterns and test conditions, and marks the chip as good or bad. This set of tests (patterns and conditions) is either manually developed by engineers or generated via circuit-simulation tools. The process of generating a set of worst case tests (patterns and conditions) is very time consuming, usually trial and error for different test combinations form a long iterative loop during the design (silicon) analysis phase. The major disadvantage is that ATE can not learn, manipulate and optimize by itself based on previous tests experiences. In this paper, we proposed a computational intelligence technique (CIT) with ATE concept, such that test responses can be described by fuzzy logic, learned by neural network, and tests can be optimized automatically by genetic algorithm. Our experimental results demonstrate an excellent efficiency using ATE-CIT during the design analysis phase.