Title :
Characterization and optimization of inorganic spin on glass process for inter-metal dielectric using field emission scanning electron microscopy
Author :
Hashim, Uda ; Ayub, Ramzan Mat
Author_Institution :
MIMOS Semicond., Kuala Lumpur, Malaysia
Abstract :
Spin on Glass (SOG), an interlayer dielectric material applied in inorganic liquid form to fill narrow gaps in the subdielectric surface for planarization, is an alternative to silicon dioxide using CVD processes and CMP processes. SOG has similar electrical properties with SiO2 as an intermetal dielectric layer. In this experiment the main features looked for are cracking, gaps, conformity and smoothness. In this respect, an experiment was setup and three different SOG process schemes were investigated. The first and the third scheme executed were using the same SOG process procedure but the SOG liquid was spun on at two different speed, 2600 and 700 rpm respectively. Whereby the second scheme again followed the same SOG process procedure as the first scheme but repeated three times for thicker SOG. The result obtained indicated that the Spin on Glass process was optimized using the third scheme and the results achieved are no cracks, no gaps and smooth features. Slow ramping rate couple with single SOG process was found to be the best scheme for SOG to smoothness the topography of the intermetal dielectric. In this scheme, SOG was spun on at the speed of 700 rpm and the sequence of the temperature treatment was 80°C, 150°C and 250°C using hotplate on the SOG machine and 400°C using vertical furnace. The result revealed that SOG spin speed at 2600 rpm was too high for SOG to adequately fill the gaps. Multiple SOG process to increase the thickness is not possible due to the cracking that occurs because of the thermal stress.
Keywords :
CVD coatings; chemical mechanical polishing; dielectric materials; field emission electron microscopy; glass; permittivity; planarisation; scanning electron microscopy; silicon compounds; surface morphology; surface topography; thermal stress cracking; 150 degC; 250 degC; 400 degC; 80 degC; CMP processes; CVD; cracking; electrical properties; field emission scanning electron microscopy; glass process; inorganic spin; inter-metal dielectrics; interlayer dielectric material; intermetal dielectric layer; narrow gaps; planarization; silicon dioxide; spin on glass; subdielectric surface; thermal stress; topography; Dielectric materials; Electron emission; Glass; Planarization; Scanning electron microscopy; Silicon compounds; Surface cracks; Surface topography; Temperature; Thermal stresses;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217871