14.4mW 10Gbps CMOS limiting amplifier with local DC offset cancellers

A low-power limiting amplifier (LA) with DC offset cancellers (DCOCs) using local feedback loops is presented for D-band wireless transceivers. The number of cascaded stages of amplifiers is set to minimize the gain-bandwidth product (GBW) of each amplifier that has the required bandwidth to realize low power dissipation. The capacitance used in each DCOC is reduced by the local feedback loops. In addition, the area used by the capacitors in each DCOC is reduced by arranging metal-oxide-metal (MOM) capacitors on MOS capacitors. Moreover, a push-pull-type topology using only NMOSs is used as an output buffer to reduce the power dissipation. Furthermore, an inductive peaking technique is used for amplifiers to realize a large bandwidth. The proposed LA has been fabricated by a 40nm CMOS process. It has a differential voltage gain of 45dB, a bandwidth of approximately 6.5GHz, a power dissipation of 14.4mW, and a circuit area of 0.15mm². It can operate with a data rate of 10Gbps.