Behavioral synthesis of datapaths with low leakage power

As technology scales down, and CMOS circuits are powered by lower supply voltages, standby leakage current becomes dominant. We present a behavioral synthesis framework for the design of datapaths with low leakage power. Our technique employs the MTC-MOS circuit design style as the basis for standby leakage power minimization. A parameterized register transfer level MTC-MOS (multi threshold CMOS) module library has been developed. MTC-MOS technology provides the capability to gate the supply voltage to the modules during idle times. Leakage power management techniques have been developed which can be applied during behavioral synthesis of the data-path. A resource allocation algorithm based on clique partitioning has also been developed for optimal allocation of registers and functional units for low leakage power. We observed up to 31.91% savings in module-wise leakage power. Shutting down modules during idle times also resulted in minimization of overall power by 34.2%.