DocumentCode
1808730
Title
Maximization of fault detection in IC testing
Author
Ali, Liakot ; Sidek, Roslina ; Aris, Ishak ; Ali, Mohd Alauddin Mohd ; Suparjo, Bambang Sunaryo
Author_Institution
Dept. of Electr. & Electron. Eng., Univ. Putra Malaysia, Selangor, Malaysia
fYear
2002
fDate
19-21 Dec. 2002
Firstpage
557
Lastpage
560
Abstract
A new era began in microelectronics with the advent of integrated circuit (IC) technology. With dramatic improvement of integration technology, the complexities of IC testing has increased and become much more acute. Fault simulation technique for maximization of fault detection in IC testing is presented in this paper. Experiments on ISCAS bench-mark circuits has been conducted and it has been shown that quality test pattern can be generated using proper seed for the pattern generator, which can significantly improve fault coverage and reduce the time in testing IC.
Keywords
benchmark testing; integrated circuit testing; IC testing; benchmark testing; integrated circuit testing; Circuit faults; Circuit simulation; Circuit testing; Costs; Electrical fault detection; Electronic equipment testing; Fault detection; Integrated circuit technology; Integrated circuit testing; Test pattern generators;
fLanguage
English
Publisher
ieee
Conference_Titel
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN
0-7803-7578-5
Type
conf
DOI
10.1109/SMELEC.2002.1217885
Filename
1217885
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