Maximization of fault detection in IC testing

A new era began in microelectronics with the advent of integrated circuit (IC) technology. With dramatic improvement of integration technology, the complexities of IC testing has increased and become much more acute. Fault simulation technique for maximization of fault detection in IC testing is presented in this paper. Experiments on ISCAS bench-mark circuits has been conducted and it has been shown that quality test pattern can be generated using proper seed for the pattern generator, which can significantly improve fault coverage and reduce the time in testing IC.