• DocumentCode
    1808985
  • Title

    8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes

  • Author

    Sharma, Vibhu ; Cosemans, Stefan ; Ashouei, Maryam ; Huisken, Jos ; Catthoor, Francky ; Dehaene, Wim

  • Author_Institution
    ESAT-MICAS Lab., K.U. Leuven, Leuven, Belgium
  • fYear
    2011
  • fDate
    12-16 Sept. 2011
  • Firstpage
    531
  • Lastpage
    534
  • Abstract
    This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.
  • Keywords
    CMOS memory circuits; low-power electronics; random-access storage; wireless sensor networks; 8T SRAM; LP CMOS; SRAM macro; charge limited sequential sense amplifier; embedded SRAM; low energy consumption; mimicked negative bit-lines; wireless sensor nodes; Calibration; Computer architecture; Energy consumption; Microprocessors; Random access memory; Temperature measurement; Transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2011 Proceedings of the
  • Conference_Location
    Helsinki
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4577-0703-2
  • Electronic_ISBN
    1930-8833
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2011.6044939
  • Filename
    6044939
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1808985