SRAM Array Yield Estimation under Spatially-Correlated Process Variation

In this paper we propose a systematic method to estimate SRAM array yield considering spatially-correlated process variation. Although many parameter variations have been shown to be spatially-correlated, this phenomenon has been neglected in SRAM yield estimation due to its small impact for small SRAMs. However, its impact on array yield is significant for SRAM arrays of realistic sizes. In this paper we show that three ways in which the spatially-correlated term can be simplified to use existing approaches all lead to high levels of inaccuracy. In particular even the closest yield estimate for 32KB SRAM has more than 20% error. To rectify this we develop a new two-stage SRAM array yield estimation framework that accurately considers spatial correlation. In our approach, first the correlated variation terms are sampled at the array level to remove cell-to-cell dependency. Then we estimate cell yield using our innovative simulation-reusing scheme which dramatically decreases the number of SPICE-like circuit simulations. To the best of our knowledge, this is the first method that can efficiently and accurately estimate SRAM array yield considering spatial correlation.