DocumentCode :
180933
Title :
An Efficient Diagnosis Pattern Generation Procedure to Distinguish Stuck-at Faults and Bridging Faults
Author :
Cheng-Hung Wu ; Kuen-Jong Lee
Author_Institution :
Dept. of EE, Nat. Cheng Kung Univ., Tainan, Taiwan
fYear :
2014
fDate :
16-19 Nov. 2014
Firstpage :
306
Lastpage :
311
Abstract :
Fault Diagnosis is a critical process to identify the locations of physical defects in advanced integrated circuits. Current diagnosis tools often report multiple types of faults as defect candidates. Thus an efficient method to distinguish different types of faults is highly desired. Stuck-at and bridging faults are two most commonly used DC fault models during diagnosis. In this paper we present an efficient diagnosis pattern generation procedure to distinguish stuck-at faults and bridging faults. Two major techniques are proposed. The first one is a fault-inactivation method (FIM) that can quickly distinguish most fault pairs by inactivating one fault while detecting the other in each fault pair. The second one is a fault-types-transformation method (FTTM) that can transform the problem of distinguishing a stuck-at fault and a bridging fault into the problem of detecting a stuck-at fault. Both methods involve only one copy of the original circuit and require only an ordinary ATPG tool for stuck-at faults. Furthermore, both methods can deal with multiple fault pairs at a time and thus not only is the required CPU time small but also the dynamic test compaction capability of the ATPG tool can be utilized. Experiments on a large number of randomly selected fault pairs in ISCAS´89 and IWLS´05 benchmark circuits have been carried out. The results show that the FIM can distinguish about 91.9% of distinguishable fault pairs quickly and the FTTM can distinguish all other distinguishable fault pairs and identify all equivalent fault pairs. The average ratio of the number of diagnosis patterns over that of the test patterns for stuck-at faults is only 0.64. On average, one diagnosis pattern can distinguish 10.89 fault pairs.
Keywords :
automatic test pattern generation; benchmark testing; fault diagnosis; integrated circuit reliability; integrated circuit testing; integrated logic circuits; logic testing; ATPG tool; CPU time; DC fault model; FIM; FTTM; ISCAS´89 benchmark circuit; IWLS´05 benchmark circuit; advanced integrated circuit; bridging fault; defect candidate; diagnosis pattern generation procedure; diagnosis tool; dynamic test compaction capability; fault diagnosis; fault-inactivation method; fault-types-transformation method; multiple fault pair; physical defect; randomly selected fault pair; stuck-at fault; Automatic test pattern generation; Central Processing Unit; Circuit faults; Fault diagnosis; Integrated circuit modeling; Logic gates; Multiplexing; Fault diagnosis; bridging faults; distinguishing multiple types of faults; stuck-at-faults;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2014 IEEE 23rd Asian
Conference_Location :
Hangzhou
ISSN :
1081-7735
Type :
conf
DOI :
10.1109/ATS.2014.56
Filename :
6979118
Link To Document :
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