A Case Study on Implementing Compressed DFT Architecture

Scan Compression has become the default design-for-test (DFT) methodology for achieving high quality test at lower costs. Just as scan matured over a span of 40 years we are now observing Scan Compression improving and adapting to the needs of current designs. In this paper we present an industrial case study demonstrating how the DFT flows are impacted in the presence of compression logic for test. We develop various DFT architectures using the zScan compression technology and discuss the pros and cons of each flow w.r.t. Pin limited test and modular DFT insertion. We also show that the decisions of pin count and scan chain count dramatically impact the final QoR i.e., Test application time and test data volume required to test the chip.