Title :
Circuit-aware device reliability criteria methodology
Author :
Ryan, J.T. ; Wei, L. ; Campbell, J.P. ; Southwick, R.G. ; Cheung, K.P. ; Oates, A.S. ; Wong, H.-S.P. ; Suehle, J.
Author_Institution :
Semicond. Electron. Div., NIST, Gaithersburg, MD, USA
Abstract :
Meeting reliability requirements is an increasingly more difficult challenge with each generation of CMOS technology. The disconnection between conventional one-size-fits-all reliability specifications and the wide range of circuit applications might be a huge waste of resources. By taking into consideration circuit-level figures of merit, a novel methodology to establish device reliability criteria that reflects real-world operation of devices in circuits is proposed and demonstrated. This “circuit-aware” methodology makes a real step toward realizing the goal of application-aware reliability standards which do not require additional measurements. The beauty is its simplicity - a simple transformation to solve an important problem. The simplicity makes it attractive as a standard methodology.
Keywords :
CMOS integrated circuits; integrated circuit reliability; CMOS technology; application-aware reliability standard; circuit application; circuit-aware device reliability criteria methodology; circuit-aware methodology; circuit-level figures of merit; reliability requirement; reliability specification; Degradation; Delay; Hot carriers; Integrated circuit reliability; Stress;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044955