Random number generator architecture and VLSI implementation

Security protocols and encryption algorithms are basically based on random number generators. In this paper, a new random number generator architecture is introduced. The produced number word length is equal to 160 bits. The philosophy of the architecture relies on the usage of the SHA hash function. The offered security strength of this hash function ensures the unpredictability of the produced number. Additionally, an efficient VLSI implementation for FPGA devices of the proposed system is described. The proposed architecture is a flexible solution in applications where the original physical sources of random number generators, such as electrical noise, are not available or at least not convenient. This architecture can also be used in any cryptographic algorithm and encryption/decryption system with high-speed performance.