A 4th order subsampled RF ∑Δ ADC centered at 2.4GHz with a sine-shaped feedback DAC

A 4^th order subsampled RF LC ΣΔ ADC suitable for Software Defined Radio applications is presented. The ADC is clocked at 3.2 GHz and centered at 2.4 GHz. The simplicity of the ADC architecture combined with the subsampling technique result in a significant performance enhancement and power consumption reduction. A sine-shaped feedback DAC is used, not only for its reduced sensitivity to clock jitter but also for its more convenient frequency response to subsampled ΣΔ ADCs. An efficient algorithm for the tuning and calibration of the LC-based loop filter is presented. The ADC is implemented in a standard 130 nm CMOS technology. It achieves a 51 dB SFDR and a 40 dB SNDR in a 25 MHz BW and consumes only 19 mW from a 1.2 V supply.