DocumentCode :
1809551
Title :
Register-based reordering networks for matrix transpose
Author :
Takala, Jarmo H. ; Järvinen, Tuomas S. ; Nikara, Jari A.
Author_Institution :
Inst. of Digital & Comput. Syst., Tampere Univ. of Technol., Finland
Volume :
4
fYear :
2002
fDate :
2002
Abstract :
In array processors, data reordering is often needed to perform the computations in correct order. Matrix transpose is such a reordering operation used, e.g., in block-based video coding implementations. In this paper, a parameterized decomposition of the permutation matrix performing 2k × 2k matrix transpose is derived. A systematic approach to design register-based reordering units based on the decomposition is proposed where the number of ports, 2q, can be varied, q ≤ k.
Keywords :
VLSI; data handling; digital signal processing chips; matrix algebra; parallel architectures; video coding; array processors; block-based video coding implementations; data reordering; digital signal processing tasks; matrix transpose; parameterized decomposition; permutation matrix; register-based reordering networks; Delay; Digital signal processing; Matrix decomposition; Multiplexing; Parallel processing; Systolic arrays; Tensile stress; Time factors; Video coding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010597
Filename :
1010597
Link To Document :
بازگشت