Title :
Assertion based verification: have I written enough properties?
Author :
Banerjee, A. ; Pal, B. ; Kamarapu, C. ; Dasgupta, P. ; Chakrabarti, P.P. ; Jha, M.
Author_Institution :
Dept. of Comput. Sci. & Eng., IIT, Kharagpur, India
Abstract :
In recent times, assertion-based verification (ABV) has become an essential component of the pre-silicon design validation flow. However, the use of ABV to validate descriptions of systems during simulation lacks a proper coverage metric. We consider the task of determining the coverage of a set of assertions against a high-level stuck-at fault model. Such a coverage analysis can aid the verification engineer to add more assertions to enhance his property suite.
Keywords :
formal specification; integrated circuit design; program verification; specification languages; ABV; assertion based verification; coverage metric; high-level stuck-at fault model; presilicon design validation flow; system description validation; Acoustical engineering; Chip scale packaging; Computational modeling; Design engineering; Electronic design automation and methodology; Fault detection; Formal languages; Hardware design languages; Monitoring; System testing;
Conference_Titel :
India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First
Print_ISBN :
0-7803-8909-3
DOI :
10.1109/INDICO.2004.1497773
