DocumentCode
1809659
Title
Assertion based verification: have I written enough properties?
Author
Banerjee, A. ; Pal, B. ; Kamarapu, C. ; Dasgupta, P. ; Chakrabarti, P.P. ; Jha, M.
Author_Institution
Dept. of Comput. Sci. & Eng., IIT, Kharagpur, India
fYear
2004
fDate
20-22 Dec. 2004
Firstpage
363
Lastpage
367
Abstract
In recent times, assertion-based verification (ABV) has become an essential component of the pre-silicon design validation flow. However, the use of ABV to validate descriptions of systems during simulation lacks a proper coverage metric. We consider the task of determining the coverage of a set of assertions against a high-level stuck-at fault model. Such a coverage analysis can aid the verification engineer to add more assertions to enhance his property suite.
Keywords
formal specification; integrated circuit design; program verification; specification languages; ABV; assertion based verification; coverage metric; high-level stuck-at fault model; presilicon design validation flow; system description validation; Acoustical engineering; Chip scale packaging; Computational modeling; Design engineering; Electronic design automation and methodology; Fault detection; Formal languages; Hardware design languages; Monitoring; System testing;
fLanguage
English
Publisher
ieee
Conference_Titel
India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First
Print_ISBN
0-7803-8909-3
Type
conf
DOI
10.1109/INDICO.2004.1497773
Filename
1497773
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