DocumentCode
1809675
Title
Complexity estimation and network synthesis based on functional smoothness and entropy measures
Author
Bhat, M.S. ; Jamadagni, H.S.
Author_Institution
Centre for electron. Design & Technol., Indian Inst. of Sci., Bangalore, India
fYear
2004
fDate
20-22 Dec. 2004
Firstpage
368
Lastpage
372
Abstract
We propose a novel method to estimate the complexity of multiple-valued logic functions based on functional smoothness and information theoretic measures. Further, we show that such complexity measures can be used to (a) estimate the area of the circuit implementation and (b) reduce the search space of potential solutions in evolvable network synthesis.
Keywords
circuit complexity; circuit optimisation; integrated logic circuits; multivalued logic; multivalued logic circuits; circuit implementation; complexity estimation; entropy measure; functional smoothness; multiple-valued logic function; network synthesis; Circuit synthesis; Counting circuits; Entropy; Libraries; Logic circuits; Logic design; Logic functions; Network synthesis; Power dissipation; Telephony;
fLanguage
English
Publisher
ieee
Conference_Titel
India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First
Print_ISBN
0-7803-8909-3
Type
conf
DOI
10.1109/INDICO.2004.1497774
Filename
1497774
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