An efficient algorithm to reduce test power consumption by scan cell and scan vector reordering

It is well known that excessive switching activity during scan testing can cause average power and peak power dissipation during test to be much higher than the normal mode operation. This obviously can cause damage to the circuit under test (CUT). One of the, major testing techniques of sequential circuits is scan testing. In this paper we present an approach to reduce power dissipation by suitably ordering the scan cells and the scan vectors. It is shown here that by carefully selecting the scan order and the vector order we can reduce significantly the number of transitions. Experiments show a reduction in transitions by as much as 25% for ISCAS´89 benchmark circuits.