A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement

Author

Kim, Tae-Ho ; Han, Jong-Seok ; Im, Sang-Soon ; Jang, Jae-Young ; Kang, Jin-Ku

Author_Institution

Inha Univ., Incheon, South Korea

fYear

2011

fDate

12-16 Sept. 2011

Firstpage

351

Lastpage

354

Abstract

This paper presents an adaptive FFE/DFE receiver with data-dependent jitter measuring algorithm. The proposed adaptive algorithm determines the compensation level by measuring the input data-dependent jitter. The adaptive algorithm is combined with a CDR phase detector. The receiver is fabricated in a 0.13-μm CMOS technology and the compensation range of equalization is up to 26 dB at 2GHz. Test chip is verified for 40-inch FR4 trace and 53-cm FPC (Flexible Printed Circuit) channel. The receiver occupies 440μm × 520μm, and power dissipation is 49mW (excluding I/O buffers) from a 1.2-V supply.

Keywords

CMOS integrated circuits; adaptive equalisers; decision feedback equalisers; integrated circuit testing; jitter; radio receivers; CDR phase detector; CMOS technology; adaptive FFE/DFE receiver; bit rate 4 Gbit/s; compensation level; compensation range; data-dependent jitter measurement; decision-feedback equalizer; equalization; feed-forward equalizer; flexible printed circuit; input data-dependent jitter; power 49 mW; power dissipation; size 0.13 mum; test chip; voltage 1.2 V; Adaptive algorithms; CMOS integrated circuits; Clocks; Decision feedback equalizers; Detectors; Jitter; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

ESSCIRC (ESSCIRC), 2011 Proceedings of the

Conference_Location

Helsinki

ISSN

1930-8833

Print_ISBN

978-1-4577-0703-2

Electronic_ISBN

1930-8833

Type

conf

DOI

10.1109/ESSCIRC.2011.6044979

Filename

6044979