Title :
A 6.7-ENOB, 500-MS/s, 5.1-mW dynamic pipeline ADC in 65-nm SOI CMOS
Author :
Nguyen, Ray ; Raynaud, Christine ; Cathelin, Andreia ; Murmann, Boris
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA
Abstract :
A 6.7-ENOB, 500-MS/s pipeline ADC is realized using low-power charge pump-like dynamic gain stages operating with incomplete transient settling. The experimental converter occupies an active area of 0.02 mm2 in 65-nm SOI CMOS and dissipates 5.1 mW from a 1.2-V supply. It achieves an SNDR of 41.5 dB for inputs near Nyquist, corresponding to a figure of merit of 98 fJ/conv.-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; low-power electronics; silicon-on-insulator; SOI CMOS; dynamic pipeline ADC; low-power charge pump-like dynamic gain stages; power 5.1 mW; size 65 nm; voltage 1.2 V; CMOS integrated circuits; Capacitance; Clocks; Gain; Logic gates; Noise; Pipelines;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044981
