DocumentCode
1810372
Title
Vector-radix DCT/IDCT implementation for MPEG DSP
Author
Liu, Muye Korley
Author_Institution
TS Electron. Corp., Plano, TX, USA
Volume
1
fYear
1996
fDate
14-18 Oct 1996
Firstpage
641
Abstract
This paper presents a hardware architecture and VHDL implementation of the vector-radix DCT/IDCT algorithm. This architecture is generic for both DCT and IDCT. A high speed 2-D video IDCT and a low cost 1-D audio DCT implementations are discussed to illustrate the exceptional hardware performance particularly for MPEG applications
Keywords
VLSI; audio coding; code standards; digital arithmetic; digital signal processing chips; discrete cosine transforms; hardware description languages; inverse problems; telecommunication standards; transform coding; video coding; MPEG DSP; MPEG applications; VHDL implementation; VLSI; hardware architecture; hardware performance; high speed 2D video IDCT; low cost 1D audio DCT; vector-radix DCT/IDCT implementation; Costs; Digital signal processing; Discrete cosine transforms; Equations; Frequency domain analysis; Hardware; Multimedia systems; Neural networks; Signal analysis; Signal processing algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing, 1996., 3rd International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-2912-0
Type
conf
DOI
10.1109/ICSIGP.1996.567345
Filename
567345
Link To Document