Title :
Comparative analysis of double-edge versus single-edge triggered clocked storage elements
Author :
Nedovic, Nikola ; Aleksic, Marko ; Oklobdzija, Vojin G.
Author_Institution :
Adv. Comput. Syst. Eng. Lab., California Univ., Davis, CA, USA
Abstract :
We present a comparison of Double-Edge Triggered clocked Storage Elements (DETSE) with their single-edge triggered counterparts in terms of delay and power consumption. In general, Latch-Mux based DETSE perform better then their single-edge counterparts while double-edge triggered flip-flops exhibit performance degradation. Up to 15% improvement in Energy-Delay Product (EDP) of Latch-Mux designs is achieved when using DETSE. The presented results indicate that the use of DETSE is a good choice when low-power operation is required.
Keywords :
CMOS logic circuits; delays; flip-flops; logic design; low-power electronics; clock frequency; delay; double-edge triggered clocked storage elements; double-edge triggered flip-flops; energy-delay product; latch-mux designs; low-power operation; performance degradation; power consumption; single-edge triggered clocked storage elements; Clocks; Degradation; Delay; Energy consumption; Flip-flops; Frequency; Latches; Master-slave; Power engineering computing; Uncertainty;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010651
