DocumentCode
1810436
Title
A parallel real-time image processing system based on TMS320C40
Author
Bochun, Zhu ; Guo Chengming ; Zhaohua, Wang
Author_Institution
Beijing Univ. of Posts & Telecommun., China
Volume
1
fYear
1996
fDate
14-18 Oct 1996
Firstpage
653
Abstract
In this paper, a real-time image processing system based on the two-chip DSP TMS320C40 of Texas Instruments is introduced. The frame store is reconfigurable. This, combined with the flexible interface and powerful communication capability of TMS320C40, enables the system to be easily configured as SIMD, MIMD parallel and pipeline structures. The distortion of the image processed by several elements is avoided without additional circuits
Keywords
digital signal processing chips; image processing; interference suppression; parallel architectures; real-time systems; reconfigurable architectures; MIMD; SIMD; communication capability; distortion; flexible interface; frame store; parallel real-time image processing system; parallel structure; pipeline structure; two-chip DSP TMS320C40; Central Processing Unit; Circuits; Coprocessors; Digital signal processing; Image processing; Master-slave; Pipelines; Read-write memory; Real time systems; Telecommunications;
fLanguage
English
Publisher
ieee
Conference_Titel
Signal Processing, 1996., 3rd International Conference on
Conference_Location
Beijing
Print_ISBN
0-7803-2912-0
Type
conf
DOI
10.1109/ICSIGP.1996.567348
Filename
567348
Link To Document