A low power all-digital signal component separator for uneven multi-level LINC systems

This paper presents an all-digital signal component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm². The required phases of branch signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of -31.06 dB using 64-QAM OFDM signals can be achieved for high-efficiency UMLINC systems.