High-speed memory-saving architecture for the embedded block coding in JPEG2000

This paper presents a high-speed, memory-saving architecture for the embedded block coding algorithm in JPEG2000. The architecture is based on the proposed memory-saving algorithm that can achieve 4 K bits reduction in the memory requirement (20% less than conventional approaches) without degrading the delay of the critical path. By exploiting the characteristic that the input symbols of the arithmetic coder in JPEG200 have a highly skewed distribution, a simple renormalization strategy is adopted for the code-string register in our pipelined MQ coder design to enhance the clock rate. The overall design is fully implemented in a chip using TSMC 0.35 μm CMOS technology. The chip can operate up to 142 MHz at post-layout simulation and is capable of many applications.