Design methodology of a low power high speed CMOS ADC

Author

Maman, Neelam ; Jharia, Bhavana ; Agarwal, R.P.

Author_Institution

Dept. of Electron. & Comput. Eng., Indian Inst. of Technol., Roorkee, India

fYear

2004

fDate

20-22 Dec. 2004

Firstpage

530

Lastpage

533

Abstract

This paper presents the design of a very low-power and high-speed, with a 70-75 MS/s 8b, CMOS analog to digital converter (ADC). The design equations are solved to achieve the complete architecture of the ADC. The maximum sampling speed achieved is 75 MHz at an analog power supply of 2.5 V. Total power consumption at full speed is 24.8 mW. The ADC is implemented using 0.35 μm MOSIS BSIM3 model.

Keywords

CMOS integrated circuits; analogue-digital conversion; high-speed integrated circuits; integrated circuit design; integrated circuit modelling; low-power electronics; 0.35 micron; 2.5 V; 24.8 mW; 75 MHz; ADC; CMOS analog to digital converter; MOSIS BSIM3 model; design methodology; maximum sampling speed; Analog-digital conversion; CMOS technology; Circuits; Design methodology; Latches; Low voltage; Power engineering computing; Power supplies; Preamplifiers; Signal resolution;

fLanguage

English

Publisher

ieee

Conference_Titel

India Annual Conference, 2004. Proceedings of the IEEE INDICON 2004. First

Print_ISBN

0-7803-8909-3

Type

conf

DOI

10.1109/INDICO.2004.1497812

Filename

1497812

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1810754