Robust design with virtual tests of mixed-signal circuits in VHDL-AMS

This paper demonstrates a new time-domain behavioral model with nonideal circuit effects in VHDL-AMS to perform virtual tests for co-simulating and verifying mixed-signal circuits. This model allows designers to fulfill not only a top-down design procedure for both analog and digital circuits, but also bottom-up verification to find possible design problems in early design stages. Designers can add or delete the functions of circuit nonidealities with minimal modifications in the model to find reasonable tradeoffs between accuracy and simulation time. Design margins are also considered in the behavioral simulations to make circuits more immune to process variation. A 14-bit 2-Msamples/s Delta-Sigma A/D converter is modeled, designed, implemented and verified based on top-down and bottom-up design procedures.