DocumentCode
1811352
Title
An optimal fault-tolerant design approach for array processors
Author
Zhang, C.N. ; Bachtiar, T.M. ; Chou, W.K.
Author_Institution
Dept. of Comput. Sci., Regina Univ., Sask., Canada
fYear
1994
fDate
19-22 Dec 1994
Firstpage
348
Lastpage
353
Abstract
A systematic approach for designing fault tolerant systolic array using space/time redundancy is proposed. The approach is based upon a fault tolerant mapping theory which relates space-time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and optimal. Besides, it has the capability to compute more problem instances simultaneously without extra cost
Keywords
error detection; fault tolerant computing; systolic arrays; array processors; concurrent error detection; fault tolerant mapping theory; optimal fault-tolerant design approach; space/time redundancy; systolic array; Computer science; Costs; Error correction; Fault detection; Fault tolerance; Information science; Log periodic antennas; Redundancy; Runtime; Systolic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Parallel and Distributed Systems, 1994. International Conference on
Conference_Location
Hsinchu
Print_ISBN
0-8186-6555-6
Type
conf
DOI
10.1109/ICPADS.1994.590320
Filename
590320
Link To Document