Multiplier-less Digital Down Converter in 90nm CMOS technology

Author

Ren, Saiyu ; Billman, Steven ; Siferd, Ray

Author_Institution

Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

fYear

2011

fDate

20-22 July 2011

Firstpage

316

Lastpage

319

Abstract

A Digital Down Converter (DDC) is presented based on square wave local oscillators facilitating a multiplier-less implementation with no constraints on the sampling frequency. The DDC includes a pseudo multi-rate SINC low pass filter which exhibits better performance compared to the standard multi-stage sinc filter. The pseudo multi-rate SINC filter can be implemented with a unique cascaded integrator comb (CIC) filter to obtain the same improved performance. A 90nm CMOS design with 8 bit inputs clocked at 400MHz demonstrates a flexible, very low power/size DDC architecture for single chip digital receiver applications.

Keywords

CMOS integrated circuits; analogue-digital conversion; cascade networks; comb filters; convertors; digital signal processing chips; low-pass filters; low-power electronics; oscillators; CIC filter; CMOS design; CMOS technology; cascaded integrator comb filter; frequency 400 MHz; low power DDC architecture; low size DDC architecture; multiplier-less digital down converter; multiplier-less implementation; multistage sinc filter; pseudo multirate SINC filter; pseudo multirate SINC low pass filter; sampling frequency; single chip digital receiver; size 90 nm; square wave local oscillators; word length 8 bit; Bandwidth; Baseband; CMOS integrated circuits; Finite impulse response filter; Mixers; Power harmonic filters; Receivers;

fLanguage

English

Publisher

ieee

Conference_Titel

Aerospace and Electronics Conference (NAECON), Proceedings of the 2011 IEEE National

Conference_Location

Dayton, OH

ISSN

0547-3578

Print_ISBN

978-1-4577-1040-7

Type

conf

DOI

10.1109/NAECON.2011.6183123

Filename

6183123