Hardware optimized direct digital frequency synthesizer architecture with 60 dBc spectral purity

We introduce a novel sine-output Direct Digital Frequency Synthesizer (DDFS) architecture, optimized for hardware implementation, that achieves better than 60 dBc spectral purity from DC to the Nyquist frequency. Instead of a ROM, we use a hardware efficient phase-to-sine amplitude converter that approximates the first quadrant of the sine function with eight equal length piecewise linear segments. The converter´s complexity is significantly reduced through careful selection of the segments´ slopes and y-intercepts. The description of the synthesizer in VHDL requires less than 200 lines of code, and implementation in a X4000 series FPGA requires only 59 configurable logic blocks. The architecture is particularly suitable for low power wireless communications applications.