Title :
Sorting networks with built-in error correction
Author :
Hsu, Yuang-Ming ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A sorting network with built-in error correction is proposed in this paper. A time shared TMR scheme is used to achieve the error correcting capability. A quarter of the original sorting network based on perfect shuffle is triplicated and voted in each stage. The hardware complexity of this time shared TMR error correcting sorting network is a little more than the original sorting network. The price is that the delay time increases by a factor of 4. However, the throughput penalty can be minimized by pipelining. A technology-independent gate level analysis of hardware complexity and delay time is included in this paper. Possible variations of the basic design are also discussed
Keywords :
computational complexity; error correction; hypercube networks; built-in error correction; delay time; hardware complexity; perfect shuffle; pipelining; sorting networks; technology-independent gate level analysis; throughput penalty; time shared TMR scheme; Circuit faults; Computer errors; Computer network reliability; Delay effects; Error correction; Hardware; Pipeline processing; Redundancy; Sorting; Throughput;
Conference_Titel :
Parallel and Distributed Systems, 1994. International Conference on
Conference_Location :
Hsinchu
Print_ISBN :
0-8186-6555-6
DOI :
10.1109/ICPADS.1994.590339
