Delayed precise invalidation-a software cache coherence scheme

Software-based cache coherence scheme is very desirable in scalable multiprocessor as well as massively parallel processor designs. We propose a software-based cache coherence scheme named delayed precise invalidation. The delayed precise invalidation is based on compiler time markings of references and a hardware-based local explicit invalidation of stale data in parallel and selectively. With a small amount of additional hardware and a small set of cache management instructions, the delayed precise invalidation provides more cacheability and allows invalidation of partial elements in an array, overcoming some of the inefficiencies and deficiencies of previous schemes. A correctness proof and a qualitative performance evaluation of the proposed scheme are also presented. Finally, the simulated cache hit ratios of the delayed precise invalidation and the parallel explicit invalidation scheme are given. Simulation results show that the delayed precise invalidation outperforms the parallel explicit invalidation scheme by 1O%