Title :
FPGA implementation of a reconfigurable microprocessor
Author_Institution :
Quebec Univ., Montreal, Que., Canada
Abstract :
The implementation of an 8-b reconfigurable microprocessor (RM) in a memory-based FPGA (field programmable gate array) device (XILINX) is described. The RM is designed as an 8-b microprocessor with a complete instruction set (41), hardware and software interrupts, and a 2-Kb addressing range (11-b address bus). The author presents the tradeoffs involved in designing the architecture, the design for performance issues, and the possibilities for future development
Keywords :
field programmable gate arrays; 8 bit; ASIC; FPGA implementation; XILINX; architecture; complete instruction set; design for performance; hardware interrupts; memory-based FPGA; reconfigurable microprocessor; software interrupts; Circuits; Computer architecture; Costs; Field programmable gate arrays; Hardware; Logic gates; Manufacturing; Microprocessors; Prototypes; Reconfigurable logic;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590366
