Technology mapping and circuit depth optimization for field programmable gate arrays

A two-step technology mapping algorithm for lookup-table-type FPGAs (field programmable gate arrays) is proposed. In the first step, the technology mapper attempts to minimize the total number of TLUs (table look-ups) used and the same time to keep the length of the critical path short. Then, it is followed by a rule-based postprocessor which maximally decreases the depth of a circuit. The good results obtained are attributed to the fact that the partitioning approach employed is tightly coupled with the size of the target TLU blocks.