DocumentCode :
1813163
Title :
ESD protection circuits with novel MOS-bounded diode structures
Author :
Ker, Ming-Dou ; Chuang, Che-Hao
Author_Institution :
Integrated Circuits & Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan
Volume :
5
fYear :
2002
fDate :
2002
Abstract :
On-chip ESD protection circuits realized with novel diode structures, without the field-oxide boundary across the p/n junction, are proposed. A PMOS (NMOS) structure is especially inserted into the diode structure to form the PMOS-bounded (NMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. Without the field oxide boundary across the p/n junction of the diode structure, the proposed PMOS-bounded and NMOS-bounded diodes can sustain much higher ESD stress, especially under the reverse-biased condition. Such PMOS-bounded and NMOS-bounded diodes are fully process-compatible with general CMOS processes without additional process modification or mask layers. The ESD protection circuits designed by such new diodes, with different junction parameters, have been successfully verified in a 0.35 μm CMOS process.
Keywords :
CMOS integrated circuits; electrostatic discharge; integrated circuit design; integrated circuit measurement; integrated circuit reliability; semiconductor device breakdown; semiconductor diodes; 0.35 micron; CMOS IC ESD protection circuits; CMOS process-compatible; ESD stress; MOS-bounded diode structures; NMOS-bounded diode; PMOS-bounded diode; field oxide isolation blocking; on-chip ESD protection circuits; p/n junction field-oxide boundary; reverse-biased condition; CMOS process; CMOS technology; Circuits; Clamps; Diodes; Electrostatic discharge; Protection; Robustness; Stress; Variable structure systems;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010758
Filename :
1010758
Link To Document :
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