DocumentCode :
1813261
Title :
A new hardware efficient design for the one dimensional discrete Fourier transform
Author :
Guo, Jiun-In ; Lin, Chien-Chang
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Nat. Chung Cheng Univ., Chia Yi, Taiwan
Volume :
5
fYear :
2002
fDate :
2002
Abstract :
This paper presents a new hardware efficient design for the one-dimensional (1D) discrete Fourier transform (DFT). By combining the advantages of distributed arithmetic (DA) computation and features of the cyclic convolution, we can efficiently realize the 1D N-point DFT using small ROM modules and accumulators. To increase the ROM utilization, we first make all the N ROM modules identical and only share a ROM module in computing all the DFT outputs. Besides, we apply the ROM partition to further reduce the ROM cost with the overhead of slowing down the speeds. This hardware efficient feature is very useful in realizing the long length DFT with critical hardware requirement. Comparison results with the traditional DA-based designs show that the proposed design can reduce the ROM cost exponentially.
Keywords :
VLSI; convolution; digital signal processing chips; discrete Fourier transforms; distributed arithmetic; integrated circuit design; integrated memory circuits; logic partitioning; read-only storage; 1D N-point DFT; 1D discrete Fourier transform; DA-based designs; DFT outputs; ROM cost; ROM modules; ROM partition; ROM utilization; VLSI implementation; accumulators; critical hardware requirement; cyclic convolution; distributed arithmetic computation; hardware efficient design; long length DFT; Arithmetic; Computer science; Convolution; Costs; Design engineering; Discrete Fourier transforms; Hardware; Read only memory; Signal processing algorithms; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010762
Filename :
1010762
Link To Document :
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