Multi-gates SOI LDMOS for improved on-state performance

Author

Dawei Xu ; Xinhong Cheng ; Yuehui Yu ; Zhongjian Wang ; Chao Xia ; Duo Cao ; Qing-Tai Zhao ; Linjie Liu ; Mantl, Siegfried

Author_Institution

State Key Lab. of Functional Mater. for Inf., Shanghai Inst. of Micro-Syst. & Inf. Technol., Shanghai, China

fYear

2014

fDate

15-19 June 2014

Firstpage

175

Lastpage

178

Abstract

SOI LDMOS with multi-gates structure is proposed and fabricated. In this structure, the long gate of the conventional LDMOS (C-LDMOS) is split into four short gates. There is an n+ doped region between two adjacent short gates. The multi-gates structure enhances electric field in the channel region, leading to a higher electron velocity which will induce a larger channel current. The experimental results demonstrate that the proposed four gates LDMOS (FG-LDMOS) shows 4.5% increase in breakdown voltage, 19.2% reduction in on-state resistance and 30.5% improvement in peak transconductance compared with the C-LDMOS.

Keywords

MOSFET; silicon-on-insulator; FG-LDMOS; SOI LDMOS; channel region; four gates LDMOS; multigates structure; n+ doped region; on-state resistance; silicon-on-insulator; Electric fields; Junctions; Logic gates; Mathematical model; Performance evaluation; Resistance; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on

Conference_Location

Waikoloa, HI

ISSN

1943-653X

Print_ISBN

978-1-4799-2917-7

Type

conf

DOI

10.1109/ISPSD.2014.6856004

Filename

6856004