Ultralow specific on-resistance high voltage LDMOS with a varible-K dielectric trench

An ultra-low R_{on, sp} SOI LDMOS with an improved BV is proposed and its breakdown mechanism is investigated. The device features a variable-k dielectric trench and a P-pillar beside the trench (VK-P). The P-pillar extending from the P-body to the trench bottom not only acts as the vertical junction termination extension (JTE), but also forms an enhanced vertical RESURF (reduced surface field) structure with the N drift region. Both improve the BV and R_{on, sp}. The variable-k dielectric trench significantly enhances the electric field (E-field) in the silicon around the trench, and the low-k dielectric in the upper trench results in higher E-field strength than that of an LDMOS with SiO₂-filled trench (UK-P), thus enabling a shorter pitch to sustain a high BV. Combining the variable-k trench and the P-pillar, the VK-P LDMOS improves the BV by 74% and reduces the R_{on, sp} by 88% compared with the UK LDMOS. At the same BV, the VK-P reduces the trench width by 40% compared with UK-P LDMOS, thus saving the area. The significant improvements in the BV, R_{on, sp}, and cell pitch make the VK-P LDMOS preferable as a power device in the HVIC.