• DocumentCode
    181351
  • Title

    Verification of quasi-synchronous systems with Uppaal

  • Author

    Bhattacharyya, Siddhartha Sid

  • Author_Institution
    Advanced Technology Center, Rockwell Collins
  • fYear
    2014
  • fDate
    5-9 Oct. 2014
  • Firstpage
    1
  • Lastpage
    10
  • Abstract
    • Formal verification for a synchronous system is considerably faster and easier than for a quasi-synchronous or asynchronous systems • Uppaal´s strength is in the support for real-time capabilities with realtime clocks. • Uppaal seems to be very well suited for modeling concurrent, asynchronous components, particularly if real-time properties are of interest. • Translating AADL models into Uppaal posed several challenges. — Uppaal uses the same construct, the process, for both concurrency and modularity. — Uppaal doesn´t provide separate constructs for nested subcomponents that execute synchronously, with bounded asynchrony at the top-most level. So subcomponents had to be constrained to execute synchronously. • Additional constructs for structuring Uppaal templates would have made this easier. — Many of our safety properties are most easily specified using a pre operator to refer to the previous value of a variable. A next-state operator in Uppaal would address this need.
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Digital Avionics Systems Conference (DASC), 2014 IEEE/AIAA 33rd
  • Conference_Location
    Colorado Springs, CO, USA
  • Print_ISBN
    978-1-4799-5002-7
  • Type

    conf

  • DOI
    10.1109/DASC.2014.6979672
  • Filename
    6979672