A VLSI array processor for neural network algorithms

A chip based on a new scalable parallel systolic VLSI architecture is presented for executing the compute-bound algorithmic primitives used by search and learning algorithms in neural networks and low-level signal processing. The architecture combines high performance with a high grade of flexibility for all types and sizes of neural networks. The processor chip can be connected to form 1-D and 2-D arrays. By offering an accuracy of 16 b for input and 47 b for output data, the chip achieves 800M connections/s at 50 MHz. It is realized in 1.0-μm CMOS (610K transistors on 13.7 × 13.7 mm²) and has a total data bandwidth of 10.9 Gb/s