Timing-driven resynthesis by rescheduling and encoding

Timing-driven resynthesis for datapath-controller systems is described. Sequential optimization and scheduling are combined to meet the designer´s clock cycle time constraint, taking into account timing constraints imposed by the interactions between datapath and controller. Given a controller behavior and an initial, scheduled FSM (finite state machine) implementation, one assigns state codes and modifies its scheduling to meet the cycle time requirement. Experimental results show that significant delay improvement can be achieved with little area overhead