Synthesis of throughput-optimized multichip architectures

An optimization approach to synthesizing DSP (digital signal processing)-specific multichip architectures which maximize throughput is presented. A new integer programming (IP) model is presented that supports simultaneous scheduling, allocation, partitioning, and maximization of throughput. The IP model is used to map a DSP application to a high-speed multichip application-specific architecture. The same model supports a communication delay whenever data are transferred off of one onto the other chip. This research breaks new ground by (1) simultaneously partitioning, scheduling, allocating, and maximizing throughput in practical CPU times, (2) guaranteeing optimal multichip architectures which maximize throughput, minimize area, or minimize latency, (3) supporting interchip communication delay, and (4) providing industry with a DA tool for optimal mapping of DSP applications to high-performance multichip architectures that can readily take advantage of emerging programmable VLSI technologies