Mixed-mode simulation of phase-locked loops

Behavioral models for mixed-mode and multilevel simulation of phase-locked loops (PLLs) are described. PLLs are a difficult class of systems to evaluate using conventional circuit simulators because of the mixed analog-digital signals involved, and extensively long run times required to capture the performance. Behavioral modeling techniques and a mixed-signal simulator, the ADAMS simulator, are used to overcome these limitations. An all-analog PLL is simulated at the behavioral level to measure the lock-in characteristics as well as the tracking range. A high-speed digital PLL is simulated at the behavioral level, as well as at a multilevel using device-level models for the phase detector, to measure the lock-in time and detect false locking