Dynamic Reconfigurable Shaders with Load Balancing for Embedded Graphics Processing

The increasing demand for application specific processing on portable devices is driving the design with highly efficient hardware. Many applications are streamlined, and the delays of all streamline stages better be equalized. Unfortunately, loads at each stage of streamlined processing may vary depending on input data, making load monitoring and balancing very desirable hardware features. The aim of this paper is to solve the load-imbalance problem of heterogeneous shading processors using a dynamically reconfigurable architecture. We begin with arithmetic analysis of required computations at different processors, determining basic building blocks for assorted functional units. Next we design reconfiguration controller capable of configuring a number of these blocks into desires functional units. Then, we measure load distribution and variations of concerned processors, and design load monitor to generate reconfiguration controller stimulus. Finally, we put all these together to propose our idea. Vertex and pixel processors are used in this study, due to that number of vertices to be processed versus number of pixels has noticeable variations along time. To evaluate this idea, clock cycle-based simulation using 3Dmark05 is conducted. Silicon area and processing cycles are measured in the experiments, and results are compared against a design using the same number of (vertex+pixel) shaders under the best partition for the test workloads. As a result, the measured data show that 60% improvement in speed and 30% improvement in hardware utilization can be achieved. In addition, using 27~35% less silicon area, the same performance can be achieved. The most valuable contribution is more than area and time saving of just the involved stages: with load monitoring and balancing, delays in different streamline stages can be well balanced, squeezing out the ultimate performance of the entire system.