Title :
Full System Simulation and Verification Framework
Author :
Lin, Jing-Wun ; Wang, Chen-Chieh ; Chang, Chin-Yao ; Chen, Chung-Ho ; Lee, Kuen-Jong ; Yuan-Hua Chu ; Yeh, Jen-Chieh ; Hsiao, Ying-Chuan
Author_Institution :
Inst. of Comput. & Commun. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
In this paper, we propose a framework to develop high-performance system accelerator hardware and the corresponding software at system-level. This framework is designed by integrating a virtual machine, an electronic system level platform, and an enhanced QEMU-SystemC. The enhancement includes a local master interface for fast memory transfer, and an interrupt handling hardware for software/hardware communication that enables full system simulation. Finally, the PAC DSP core is used as examples to demonstrate the proposed framework for full system simulation.
Keywords :
integrated circuit design; performance evaluation; system-on-chip; virtual machines; QEMU-SystemC; electronic system level platform; fast memory transfer; high-performance system accelerator hardware; software/hardware communication; virtual machine; Application software; Central Processing Unit; Communication system security; Communication system software; Hardware; Microprocessors; Operating systems; System-on-a-chip; Timing; Virtual machining;
Conference_Titel :
Information Assurance and Security, 2009. IAS '09. Fifth International Conference on
Conference_Location :
Xi´an
Print_ISBN :
978-0-7695-3744-3
DOI :
10.1109/IAS.2009.253
