One-sided communication and synchronization for non-coherent memory-coupled cores

The trend towards the integration of many cores per chip will raise the demand for new many-core architectures if established multi-core techniques such as hardware implemented cache-coherence limit scalability. Parallel applications especially with dynamically changing access pattern can benefit from software supported weaker memory consistency models in combination with one-sided communication. The realization of one-sided communication through direct access of non-coherent shared memory requires flush operations and synchronization points. In this paper, we analyze the effect of low-overhead hardware-supported synchronization methods for shared memory windows with different memory models as described by the one-sided communication extensions of MPI-3. Moreover, we compare this approach with common message passing based implementation.