DocumentCode :
1814675
Title :
Improving Superscalar Instruction Dispatch And Issue By Exploiting Dynamic Code Sequences
Author :
Vajapeyam, Sriram ; Mitra, Tulika
Author_Institution :
Indian Institute of Science
fYear :
1997
fDate :
2-4 June 1997
Firstpage :
1
Lastpage :
12
Keywords :
Automation; Bandwidth; Clocks; Computer science; Computer science education; Displays; Permission; Pipelines; Registers; Supercomputers;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture, 1997. Conference Proceedings. The 24th Annual International Symposium on
Conference_Location :
Denver, Colorado, USA
ISSN :
1063-6897
Print_ISBN :
0-89791-901-7
Type :
conf
DOI :
10.1109/ISCA.1997.604515
Filename :
604515
Link To Document :
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