Robust conservative parallel HDL simulation on multi-core CPUs

Hardware description language (HDL) simulation is the fundamental means of IC verification. The complexity of modern VLSI is constantly posing serious challenges to HDL simulators. We developed a parallel HDL simulation framework in which Verilog HDL is translated into a multithreaded program for parallel execution on an ×86 multi-core processor by following a conservative parallel simulation protocol. We identified two essential problems, deterministic initialization and concurrent memory simulation, which are critical to robust logic simulation. Efficient solutions based on theoretic analysis are proposed to address the problems. Experimental results prove the effectiveness of our simulation framework.