DocumentCode
1814723
Title
Designing multiplier blocks with low logic depth
Author
Dempster, A.G. ; Dimirsoy, S.S. ; Kale, I.
Author_Institution
Univ. of Westminster, London, UK
Volume
5
fYear
2002
fDate
2002
Abstract
The depth of logic in an integrated circuit, particularly a CMOS circuit, is highly correlated both with power consumption and degraded switching speed. Hence, designs with low logic depth can aid in reducing power consumption and increasing switching speed. In this paper we demonstrate how new and modified algorithms have been used to design multiplier blocks with low logic depth and power consumption.
Keywords
CMOS logic circuits; FIR filters; IIR filters; digital arithmetic; integrated circuit design; integrated circuit modelling; logic CAD; low-power electronics; multiplying circuits; FIR filter applications; IIR filter applications; integrated circuit logic depth; low logic depth CMOS multiplier block design; low power consumption; multiplier block design algorithms; power consumption reduction; switching speed degradation; switching speed increase; synchronous CMOS circuits; Adders; Algorithm design and analysis; CMOS logic circuits; Clocks; Energy consumption; Finite impulse response filter; Frequency estimation; Logic circuits; Logic design; Switching circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010818
Filename
1010818
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